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Freescale Semiconductor, Inc.
SET FAST–READ REGISTER VALUE
This operation defines the table address that is output by
the fast–read operation. The least significant 14 bits of I/O
register 0 are copied to the fast–read register. The queue
must be empty when this instruction is executed.
FAST READ
This operation is used to output the contents of one entry
in the CAM table. The fast–read register is used to specify
the appropriate entry, and is then auto–incremented. As a re-
Bits 60 – 63 may be used for matching in ATM mode if the
application requires extra bits. The use of bits 0 – 31 for
matching is not supported in ATM mode.
MATCH DUTY CYCLE
At 50 MHz, the MCM69C432 completes a match 180 ns,
or 9 clock cycles, after assertion of the SM signal. However,
if entries need to be added to or deleted from the CAM, idle
time is needed between match output and match requests
for control port insertions and deletions. At 50 MHz, the
match duty cycle should be defined at least at 11 clock cycles
C.
I N completed, SM can be
R
operation and data output , are
O
CT bottom. If an entry with a match data
the highest value at U the
D
value smaller N than any other entry is continually added or
O the table, worst–case scenario occurs causing
dropped C
M
SE
FFFC 16 is written to the error code register, the error –
E and/or deletion is given by the formula 16,384 x MDC/(MDC
L – 10) cycles, where MDC is the match duty cycles. For
CA
ES
SET ATM MODE
RE
F
Y
B is detected when
D
virtual connection circuits (VCCs). A VCC
both the virtual path identifier (VPI) E and the virtual circuit
HI
V
RC
matches the VPI field of A a CAM entry that has all 1s as its
sult, successive execution of multiple fast–read operations (220 ns), leaving 1 clock cycle for insertions/deletions. The
will provide access to contiguous entries in the CAM table. additional clock cycle is used for holding the match data on
The CAM entry is copied to I/O registers 0 – 3, with bit 15 the MQ bus. Therefore, every 11 clock cycles, when a match
of register 3 as the most significant bit, and bit 0 of register 0
as the least significant bit. asserted.
The fast–read instruction can only be executed while the Entries are stored from least value at the top of the table to
entry queue is empty, as reflected by the queue–empty flag
being set (bit 4 of the flag register.) If this operation is
attempted while the entry queue is not empty, the value from
shifting of all other entries. The idle time, in terms of the
condition flag (bit 7) is set in the flag register, and an interrupt number cycles, needed to perform a worst–case insertion
is generated if enabled by bit 7 of the interrupt register.
example, if match requests are occurring every 11 clock
cycles:
When the MCM69C432 is placed in ATM mode, it provides
16,384 x 11 clock cycles
simultaneous searching for virtual path circuits (VPCs) and = 180,224 clock cycles
11 clock cycles – 10
At 50 MHz (20 ns per cycle)
identifier (VCI) of an incoming cell match an entry in the
CAM. A VPC match occurs when the VPI of an incoming cell = 0.00360448 sec per insert or deletion.
If both insertions and deletions are occurring
VCI. A VPC match is signalled by the assertion of the VPC
pin along with the MS pin. At 50 MHz, a match is completed
in 180 ns, whether the applied VPI/VCI belongs to a VCC or
a VPC.
The VCI match field must be defined as bits 32 – 47 of
each entry. The VPI match data must occupy bits 48 – 59.
The VPI can be limited to bits 48 – 55, if the switch handles
only User–Network Interface (UNI) protocols. The mask reg-
ister should be used to “don’t care” any unused bits beyond
the VPI field. Entering ATM mode will set bit 9 of the flag reg-
ister.
To load a VPC into the CAM table, the desired VPI value is
written (right justified) to I/O register 3, FFFF16 is written to
= 139 insertion/deletion pairs per sec (worst–case).
More typical cases consist of insertions occurring at one
end of the table and deletions occurring at the other end, or
when insertions and/or deletions take place toward the
middle of the table. The latter scenario would consist of
approximately half the total entries being shifted. The idle
time, in terms of the number of cycles, needed to perform a
typical insertion and/or deletion is given by the formula 8192
x MDC/(MDC – 10) cycles, where MDC is the match duty
cycles. For example, if match requests are occurring every
10 clock cycles:
I/O register 2 as the VCI field, the upper half of the desired
output word is written to I/O register 1, and the lower half of
the desired output word is written to I/O register 0. Then, the
8192 x 11 clock cycles
11 clock cycles – 10
= 90,112 clock cycles
“INSERT VALUE” instruction is written to the operation regis-
ter.
When performing a match operation, the VCI must be
placed in bits 0 – 15 of the MQ port. The VPI is expected on
bits 16 – 27, or bits 16 – 23 in the UNI case.
Buffered–entry mode insertions and deletions are modified
in the following way when the MCM69C432 is in ATM mode.
If you try to add a VCC with the same VPI as an existing
VPC, you overwrite the VPC. If you try to delete a VCC when
the VCC is not in the table, but a VPC with that VPI is in the
table, the VPC will be deleted.
The CAM table should never contain, simultaneously, a
VCC entry and VPC entry with matching VPIs. Violation of
this requirement may lead to unpredictable behavior.
At 50 MHz (20 ns per cycle)
= 0.00180224 sec per insert or deletion.
If both insertions and deletions are occurring
= 277 insertion/deletion pairs per sec (worst–case).
The number of insertion/deletion pairs for both cases are
depicted in Figure 3. In general, the time for an insertion or
deletion is proportional to its distance from the end of the
CAM table. That is, entries with the largest match value take
the least time to insert or delete, while entries with the small-
est values take the most time. Therefore, the effective rate of
insertion and deletion is maximized if the longest –lived
entries are placed near the beginning of the table and the
MCM69C432 ? SCM69C432
10
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